Keynote speakers
Keynote I: A European Perspective on Supercomputing |
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Prof. Mateo Valero |
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Massive computing systems will be needed to maintain competitiveness in all areas of science, engineering and business, to provide both management efficiency and computing capability. From a systems management perspective, massive installations offer an efficient platform for resource sharing and service-oriented cloud computing; from a capability perspective, they allow unprecedented performance for supercomputing applications. With top supercomputing systems reaching the PetaFlop barrier, the next challenge is to devise technology to reach, and applications to take advantage of, ExaFlop performance. Multicore chips are already here but will grow in the next decade to several hundred cores. Although these chips will be used for general-purpose computing, they will be the tera-device components of future exascale systems.
Europe is aware of the importance of having a well-structured supercomputing infrastructure, as well as the need to exchange experiences and know-how across the Union. Infrastructure projects such as the current DEISA (Distributed European Infrastructure for Supercomputing Applications) or the future PRACE (Partnership for Advanced Computing in Europe) aim at setting up such coordinated resources. PRACE, in particular, will create a world-class pan-European high performance computing service and infrastructure, managed as a single European entity. The service will include five superior supercomputing centers, strengthened by regional and national centers, working in collaboration through grid technologies. The BSC-CNS is the Spanish representative, one of five principal partners in the project (the others being Germany, France, UK and the Netherlands). The principal partner countries have agreed to contribute more to the PRACE budget, and to host the tier-0 machines which will form part of the distributed infrastructure.
Having hit the power wall, the computing market is now undergoing a shaky era of dispersion, where many kinds of multicore alternatives are being proposed as the way to develop chips with ever increasing performance capabilities. In this time of confusion we have built a tight Gordian knot, where excitement at the potential performance shown by different hardware platforms is counteracted by the fear of wasted effort in targeting applications to each and every one of those platforms. We believe that the programming model is the key component that should break the knot. With increased scale, hierarchical levels of granularity should be considered, providing the programmer with an abstract model that will be mapped to the different target platforms by their specific runtimes. Asynchrony, decoupling between logical and physical resources of all types (cores, memory, etc.), load balancing, fault tolerance, and actual understanding of the behavior of our systems are issues that will have to be addressed and supported when targeting exascale performance.
Holistic approaches with a global vision for the design of such systems should coordinate experience and techniques at all levels, from application to programming model design, runtime implementation, and architecture, both at the node and interconnect level.
The talk will first describe how the BSC and the Spanish distributed infrastructure of computers (RES) around it was set up, and discuss experiences with its operation. Then some of the European activities will be described, finishing with the BSC's vision on the major issues in designing and using the upcoming systems of the ExaFlop era.
Bio
Mateo Valero, http://personals.ac.upc.edu/mateo/, obtained his PhD from UPC. He is a professor in the Computer Architecture Department at UPC, in Barcelona. His research interests focuses on high performance architectures. He has published approximately 500 papers on these topics. He has served in the organization of more than 200 International Conferences and he has given more than 300 invited talks.He is the director of the Barcelona Supercomputing Center, the National Center of Supercomputing in Spain.
Dr. Valero has been honored with several awards. Among them, the Eckert-Mauchly Award the most important worldwide award in the field of Computer Architecture, received in 2007, by the IEEE, Institute of Electrical and Electronics Engineers and the ACM, the Association for Computing Machinery, two Spanish National awards, the 'Julio Rey Pastor' in 2001, to recognize research on IT technologies, and the 'Leonardo Torres Quevedo' in 2006, to recognize research in Engineering, by the Spanish Ministery of Science and Technology, presented by the King of Spain. In 1997, he received 'the King Jaime I' in research by the Generalitat Valenciana and presented by the Queen of Spain.
In December 1994, Professor Valero became a founding member of the Royal Spanish Academy of Engineering. In 2005 he was elected Correspondant Academic of the Spanish Royal Academy of Science and in 2006 and member of the Royal Spanish Academy of Doctors. In 2000 he became a Fellow of the IEEE. In 2002 he became an Intel Distinguished Research Fellow and a Fellow of the ACM. 'Hall of the Fame' member of the IST European Program, selected as one of the 25 most influents European researchers in IT during the period 1983-2008. He has also been named Honorary Doctor by the University of Chalmers, by the University of Belgrade and by the University of Las Palmas de Gran Canaria in Spain.
Keynote II: The Roadrunner Project and the Importance of Energy Efficiency on the Road to Exascale Computing |
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Dr. Donald Grice |
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The cost of the energy required to run ultrascale supercomputers is becoming a large portion of the operating budgets of many facilities and it has the potential of limiting the scale of computers that can be deployed. The Roadrunner project was started as a development project aimed at finding a way to scale up applications but at a significantly more efficient energy usage than the current systems. Heterogeneous core types allow single thread performance to remain high while reducing the energy required for a given computation by eliminating the circuits and associated power that are not needed for the computation. This optimizes the energy cost per operation but puts a burden on the software to deal with heterogeneous core types.
The Roadrunner system was the first to reach a sustained Petaflop on the Linpack benchmark and it involved some interesting new Hardware but the bulk of the effort was in Software development including programming models and applications. Several applications were ported to the new structure with relatively little difficulty and the expected performance and energy efficiency improvements were attained.
This talk will cover an overview of the Roadrunner project, including the fundamental Cell BE building block and the software structure and methods that were included. The success of the energy efficiency improvement has lead to a broader view of the utility of heterogeneous computing in the Computationally Intensive Workload area.
Bio
Dr. Grice is an IBM Distinguished Engineer and currently the Technical Executive for Integrated Systems Development in Systems Architecture and Design for IBM STG. He is responsible for the architecture of POWER clusters and the integration of cluster systems designs, focusing on high performance computing. Dr. Grice is also the Chief Engineer of the Roadrunner project which integrates cell and x86 technology in a hybrid blade-based architecture.Dr. Grice was formerly the Chief Engineer for the RS/6000 SP program and currently holds over 40 patents, 15 of them for technology incorporated in IBM HPC cluster designs. He joined IBM in Kingston, NY, in 1972 after graduating from Rensselaer Polytechnic Institute (RPI) with a Bachelor of Science degree in Electrical Engineering. In 1984, Dr. Grice earned his doctorate in Electrical Engineering at RPI in speech signal-processing while working at the IBM Kingston site on a voice-assisted terminal program. He was an adjunct professor at RPI for 10 years (1984-1994) teaching multi-processing microprocessor systems.
Keynote III: Computing Outside the Box |
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Dr. Ian Foster |
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The past decade has seen increasingly ambitious and successful methods for outsourcing computing. Approaches such as utility computing, on-demand computing, grid computing, software as a service, and cloud computing all seek to free computer applications from the limiting confines of a single computer. Software that thus runs 'outside the box' can be more powerful (think Google, TeraGrid), dynamic (think Animoto, caBIG), and collaborative (think FaceBook, myExperiment). It can also be cheaper, due to economies of scale in hardware and software. The combination of new functionality and new economics inspires new applications, reduces barriers to entry for application providers, and in general disrupts the computing ecosystem. I discuss the new applications that outside-the-box computing enables, in both business and science, and the hardware and software architectures that make these new applications possible.